1. Field of the Invention
The present invention relates generally to semiconductor fabrication methods and, more particularly, to a method of estimating line-edge-roughness and line-width roughness.
2. Description of Related Art
Semiconductor devices commonly include elements having shapes and sizes that unavoidably deviate from their ideal reference forms. Measurement and characterization of such deviation can be an important technique for controlling yield and reliability of a semiconductor production process. As one example, a semiconductor device, especially one comprising repetitive patterns such as with memory devices, may contain patterns of closely-spaced parallel conducting lines that must be physically isolated from each other. The edges of these lines, although nominally smooth and straight, are inevitably somewhat rough and irregular when viewed at very small scales. The roughness and irregularity can be represented mathematically with measurements of line edge roughness (LER) and line width roughness (LWR).
Generally, greater degrees of LER and LWR correspond with greater levels of unreliability and, consequently, to lower yields in semiconductor production processes. Accordingly, methods of monitoring and analyzing LER/LWR are important aspects of semiconductor production processes. Estimates of LER and LWR can be obtained using methods known in the art in cases where images of the parallel lines are obtained under conditions that are uniform from one region to another. However, when pre-layers are introduced in portions of an integrated circuit pattern, the characteristics of the pre-layers tend to complicate, confuse, obscure, and distort the estimation of LER and LWR.
A need thus exists in the prior art for a method of measurement of LER and LWR that is adapted to account for pre-layers. A further need exists for a method of relating line quality to yield and reliability of an integrated circuit when pre-layers are present.